Semiconductor devices have been highly integrated for satisfying high performance and low manufacture cost requirements that have been requested by users. Because integration of semiconductor devices may be an important factor in determining product price, highly integrated semiconductor devices are increasingly demanded. Integration of typical two-dimensional or planar semiconductor devices is primarily determined by the area occupied by a unit memory cell, such that it may be greatly influenced by the level of technology used for forming fine patterns. However, the processing equipment used to increase pattern fineness may be expensive and, therefore, may set a practical limitation on increasing the integration of two-dimensional or planar semiconductor devices.
To overcome such limitations, three-dimensional semiconductor memory devices having three-dimensionally arranged memory cells have been proposed. A method of fabricating the three-dimensional semiconductor memory device may include stacking thin layers on a substrate and selectively wet etching a portion of the stacked thin layers. In this case, the wet etching process may be performed using an etchant having an etch selectivity.